1) Field of the Invention
Embodiments of the present invention relate to a clock control device, and more particularly to a technology for reducing the amount of current consumption when a semiconductor device operates at a high speed.
2) Description of the Related Art
With the increasing integration degree of semiconductor memory devices, semiconductor memory devices have also been continuously improved to increase the operation speed. In order to increase operation speeds of semiconductor memory devices, synchronous memory devices capable of operating by synchronizing with an external clock of a memory chip have been recently proposed and developed.
A representative example of a synchronous memory device is a single data rate (SDR) synchronous memory device that is synchronized with a rising edge of an external clock of a memory device such that one data piece can be input and/or output at one data pin during one period of the clock.
However, the SDR synchronous memory device has difficulty in satisfying a high-speed operation of the system. In order to solve the problem of the SDR synchronous memory device, a double data rate (DDR) synchronous memory device capable of processing two data pieces during one clock period has been proposed.
Two contiguous data pieces are input and output through respective data input/output (I/O) pins of the DDR synchronous memory device, such that the two contiguous data pieces are synchronized with a rising edge and a falling edge of an external input clock. Therefore, although a clock frequency of the DDR synchronous memory device is not increased, the DDR synchronous memory device may have a bandwidth that is at least two times larger than that of the SDR synchronous memory device, such that the DDR synchronous memory device can operate at a higher speed than the SDR synchronous memory device.
The DDR synchronous memory device is configured to use a multi-bit prefetching scheme capable of simultaneously processing multiple bits (multi-bit) of data pieces. The multi-bit prefetch scheme synchronizes sequential input data pieces with a data strobe signal such that the input data pieces can be arranged in parallel to one another. Thereafter, the multi-bit prefetch scheme can simultaneously store the arranged multi-bit data pieces upon receiving a write command synchronized with an external clock signal.
However, it is important for a low-power DDR synchronous memory device operated at a low power-supply voltage to reduce the amount of current consumption. For this purpose, the low-power DDR synchronous memory device should operate an internal clock only within a specific interval required for reducing an operation current. That is, the conventional low-power DDR synchronous memory device operates an internal clock only during a suitable time upon receiving a command using a setup time of a chip select signal, and disables the internal clock during the remaining time intervals other than the suitable time, such that it reduces the operation current.
However, as the operation frequency of the memory device gradually increases, each of a setup time and a hold time of the chip select signal is applied for a short period of time. In the case of a manufactured product operated at a low power-supply voltage, a defective margin frequently occurs between an address and an operation command such that the product has difficulty in controlling an internal clock only using the setup time of the chip select signal.